The present invention is generally related to the manufacture of integrated circuits and, more particularly, is related to a system and method for constructing a profile of a structure in an integrated circuit.
In the manufacture of integrated circuits, many structures such as circuit elements are created that are microscopic in size. These are generally created using various well known techniques such as photolithography. Photolithography generally involves the creation of a circuit pattern that is photographed and reduced to a negative called the photomask that has a desired final size. Next, light is generally passed through the photomask onto a wafer that comprises a semiconductor material that is coated with photoresistive material. For those locations upon which the light falls, the composition of the photoresistive material is changed. Thereafter, the photoresistive material that has been subjected to light is washed off and, finally, the semiconductor material is subjected to an etching solution that eats away the surface not protected by the photoresistive material. The structures that remain in the semiconductor material make up the resulting circuit pattern on the surface of the wafer.
As a manufacturing method, photolithography has seen great advances in more recent times. Where the first integrated circuits made could only include a relatively small number of circuit elements, currently integrated circuits can be manufactured with millions of circuit elements. This is due, in part, to the fact that advancements in photolithography have resulted in greater resolution and corresponding circuit density. Accompanying the greater density of circuits has been a steady increase in the speeds at which these circuits operate.
Even with advancements with the density and speed of operation of integrated circuits, current manufacturing processes are not without problems. Specifically, from time to time some structures such as conductive pathways may not meet required specifications in terms of size and cross-sectional dimensions among other parameters. Unfortunately, it can be rather difficult and expensive to determine whether the specific size and/or cross-section of a particular structure meets acceptable standards.
In light of the foregoing, the present invention provides a system and method for profiling a structure in an integrated circuit to determine the structural dimensions. In one embodiment, the system comprises a processor circuit that includes a processor electrically coupled to a local interface and a memory electrically coupled to the local interface, where the local interface comprises, for example, a data bus and an associated control bus. The system further comprises a critical dimension scanning electron microscope (CD-SEM) having a signal output electrically coupled to the local interface and operating logic stored on the memory and executable by the processor. The operating logic comprises logic to logic to execute a scan of a structure in an integrated circuit using the SEM, logic to store a first derivative waveform in the memory, the first derivative waveform being generated from a dimensional waveform that is generated from the scan, and, logic to generate a profile of the structure from the first derivative waveform.
The present invention can also be viewed as providing a method for profiling a structure in an integrated circuit. In this regard, the method can be broadly summarized by the following steps: measuring the structure with a scanning electron microscope (SEM) to generate a first derivative waveform, and, generating a profile of the structure from the first derivative waveform.